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52511hkim 20110419-s00003 no.a1955-1/28 ver.1.00 LC87FBL08A overview the sanyo LC87FBL08A is an 8-bit microcomputer that, centered around a cpu running at a minimum bus cycle time of 83.3ns, integrates on a single chip a number of hardware features such as 8k-byte flash rom (on-board- programmable), 256-byte ram, an on-chip-debugger, sophisticated 16-bit timers/counters (may be divided into 8-bit timers), a 16-bit timer/counter (may be divided into 8-bit timers/counters or 8-bit pwms), two 8-bit timers with a prescaler, a base timer serving as a time-of-day clock, an asynchronous/synchronous sio interface, two 12-bit pwm channels, a 12-bit/8-bit 11-channel ad converter, a system cloc k frequency divider, an inte rnal reset and a 17-source 9-vector interrupt feature. features ? flash rom ? capable of on-board programming with wide range (2.7 to 5.5v) of voltage source. ? block-erasable in 128 byte units ? writable in 2-byte units ? 8192 8 bits ? ram ? 256 9 bits ? minimum bus cycle ? 83.3ns (12mhz at v dd =2.7v to 5.5v) note: the bus cycle time here refers to the rom read speed. ordering number : ena1955 cmos ic 8k-byte from and 256-byte ram integrated 8-bit 1-chip microcontroller * this product is licensed from silicon storage te chnology, inc. (usa), and manufactured and sold by sanyo semiconductor co., ltd. specifications of any and all sanyo semiconductor co.,l td. products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer ' s products or equipment. to verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer ' sproductsor equipment. any and all sanyo semiconductor co.,ltd. products described or contained herein are, with regard to "standard application", intended for the use as general el ectronics equipment (home appliances, av equipment, communication device, office equipment, industrial equ ipment etc.). the products mentioned herein shall not be intended for use for any "special application" (medica l equipment whose purpose is to sustain life, aerospace instrument, nuclear control device, burning appliances, t ransportation machine, traffic signal system, safety equipment etc.) that shall require extremely high level of re liability and can directly threaten human lives in case of failure or malfunction of the product or may cause har m to human bodies, nor shall they grant any guarantee thereof. if you should intend to use our products for app lications outside the standard applications of our customer who is considering such use and/or outside the scope of our intended standard applications, please consult with us prior to the intended use. if there is n o consultation or inquiry before the intended use, our customer shall be solely responsible for the use.
LC87FBL08A no.a1955-2/28 ? minimum instruction cycle time ? 250ns (12mhz at v dd =2.7v to 5.5v) ? ports ? normal withstand voltage i/o ports ports i/o direction can be designated in 1-bit units 17 (p1n, p20, p21,p30, p31, p70 to p73, cf2/xt2) ports i/o direction can be designated in 4-bit units 8 (p0n) ? dedicated oscillator ports/input ports 1 (cf1/xt1) ? reset pin 1 ( res ) ? power pins 3 (v ss 1, v ss 2, v dd 1) ? timers ? timer 0: 16-bit timer/counter with a capture register. mode 0: 8-bit timer with an 8-bit programmab le prescaler (with an 8-bit capture register) 2 channels mode 1: 8-bit timer with an 8-bit programmable prescaler (with an 8-bit capture register) + 8-bit counter (with an 8-bit capture register) mode 2: 16-bit timer with an 8-bit programma ble prescaler (with a 16-bit capture register) mode 3: 16-bit counter (with a 16-bit capture register) ? timer 1: 16-bit timer/counter that supports pwm/toggle outputs mode 0: 8-bit timer with an 8-bit prescal er (with toggle out puts) + 8-bit timer/ counter with an 8-bit pres caler (with toggle outputs) mode 1: 8-bit pwm with an 8-bit prescaler 2 channels mode 2: 16-bit timer/counter with an 8-bit prescaler (with toggle outputs) (toggle outputs also possible from the lower-order 8 bits) mode 3: 16-bit timer with an 8-bit prescaler (with toggle outputs) (the lower-order 8 bits can be used as pwm) ? timer 6: 8-bit timer with a 6-bit prescaler (with toggle outputs) ? timer 7: 8-bit timer with a 6-bit prescaler (with toggle outputs) ? base timer 1) the clock is selectable from the subclock (32.768khz crystal oscillation), system clock, and timer 0 prescaler output. 2) interrupts are programmable in 5 different time schemes ? sio ? sio1: 8-bit asynch ronous/synchronous serial interface mode 0: synchronous 8-bit serial i/o (2- or 3-wire configuration, 2 to 512 tcyc transfer clocks) mode 1: asynchronous serial i/o (half-duplex, 8 data bits, 1 stop bit, 8 to 2048 tcyc baudrates) mode 2: bus mode 1 (start bit, 8 data bits, 2 to 512 tcyc transfer clocks) mode 3: bus mode 2 (start detect, 8 data bits, stop detect) ? ad converter: 12 bits/8 bits 11 channels ? 12 bits/8 bits ad converter resolution selectable ? pwm: multifrequency 12-bit pwm 2 channels ? remote control receiver circuit (sharing pins with p73, int3, and t0in) ? noise rejection function (noise filter time constant selectable from 1 tcyc, 32 tcyc, and 128 tcyc) ? clock output function ? capable generating clock outputs with a frequency of 1/1, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64 of the source clock selected as the system clock. ? capable generating the source clock for the subclock ? watchdog timer ? capable generating an internal reset on an overflow of a timer running on the low- speed rc oscillator clock or subclock. ? operating mode at standby is selectable from 3 modes (continue counting/stop operation/stop counting with a count value held).
LC87FBL08A no.a1955-3/28 ? interrupts ? 17 sources, 9 vector addresses 1) provides three levels (low (l), high (h), and highest (x )) of multiplex interrupt control. any interrupt requests of the level equal to or lower than the current interrupt are not accepted. 2) when interrupt requests to two or more vector addresses occur at the same time, the interrupt of the highest level takes precedence over the other interrupts. for interrupts of the same level, the interrupt into the smallest vector address takes precedence. no. vector address level interrupt source 1 00003h x or l int0 2 0000bh x or l int1 3 00013h h or l int2/t0l/int4 4 0001bh h or l int3/int5/base timer 5 00023h h or l t0h 6 0002bh h or l t1l/t1h 7 00033h h or l none 8 0003bh h or l sio1 9 00043h h or l adc/t6/t7/pwm4, pwm5 10 0004bh h or l port 0 ? priority levels x > h > l ? of interrupts of the same level, the one with the smallest vector address takes precedence. ? subroutine stack levels: 128levels (the stack is allocated in ram.) ? high-speed multiplication/division instructions ? 16 bits 8 bits (5 tcyc execution time) ? 24 bits 16 bits (12 tcyc execution time) ? 16 bits 8 bits (8 tcyc execution time) ? 24 bits 16 bits (12 tcyc execution time) ? oscillation circuits ? internal oscillation circuits low-speed rc oscillation circuit : for system clock (100khz) medium-speed rc oscillation circuit : for system clock (1mhz) frequency variable rc oscillation circuit : for system clock (8mhz) ? external oscillation circuits hi-speed cf oscillation circuit: for system clock, with internal rf low speed crystal oscillation circuit: for low- speed system clock, with internal rf 1) the cf and crystal oscillation circuits share the same pins. the active circuit is selected under program control. 2) both the cf and crystal oscillator circuits stop operatio n on a system reset. after reset is released, oscillation is stopped so start the oscillation operation by program. ? system clock divider function ? can run on low current. ? the minimum instruction cycle selectable from 300ns, 600ns, 1.2 s, 2.4 s, 4.8 s, 9.6 s, 19.2 s, 38.4 s, and 76.8 s (at a main clock rate of 10mhz). ? internal reset function ? power-on reset (por) function 1) por reset is generated only at power-on time. 2) the por release level can be selected from 4 levels (2.57v, 2.87v, 3.86v, and 4.35v) through option configuration. ? low-voltage detection reset (lvd) function 1) lvd and por functions are combined to generate resets when power is turned on and when power voltage falls below a certain level. 2) the use or disuse of the lvd function and the low voltage threshold level (3 levels: 2.81v, 3.79v, 4.28v) can be selected by optional configuration.
LC87FBL08A no.a1955-4/28 ? standby function ? halt mode: halts instruction execution while allowing the peripheral circuits to continue operation. 1) oscillation is not halted automatically. 2) there are three ways of resetting the halt mode. (1) setting the reset pin to the low level (2) system resetting by watchdog timer or low-voltage detection (3) occurrence of an interrupt ? hold mode: suspends instruction execution and the operation of the peripheral circuits. 1) the cf, rc, and crystal oscilla tors automatically stop operation. 2) there are four ways of resetting the hold mode. (1) setting the reset pin to the lower level. (2) system resetting by watchdog timer or low-voltage detection (3) having an interrupt source established at either int0, int1, int2, int4 or int5 * int0 and int1 hold mode reset is available only when level detection is set. (4) having an interrupt source established at port 0. ? x'tal hold mode: suspends instruction execution and the opera tion of the peripheral circu its except the base timer. 1) the rc oscillator automatically stop operation. 2) the state of crystal oscillation established wh en the x'tal hold mode is entered is retained. 3) there are five ways of resetting the x'tal hold mode. (1) setting the reset pin to the low level. (2) system resetting by watchdog timer or low-voltage detection. (3) having an interrupt source established at either int0, int1, int2, int4 or int5 * int0 and int1 hold mode reset is available only when level detection is set. (4) having an interrupt source established at port 0. (5) having an interrupt source established in the base timer circuit. note: available only when x?tal oscillation is selected. ? onchip debugger ? supports software debugging with the ic mounted on the target board. ? software break point setting for debugger. ? stepwise execution on debugger. ? real time ram data monitoring function on debugger. all the ram data map can be monitored on screen when the program is running. (the ram & sfr data can be changed by screen patch when the program is running) ? two channels of on-chip debugger pins are available to be compatible with small pin count devices. dbgp0 (p0), dbgp1 (p1) ? data security function (flash versions only) ? protects the program data stored in flash memory from unauthorized read or copy. note: this data security function does not necessarily provide absolute data security. ? package form ? qfp36(7 7) : lead-/halogen-free type ? vqlp32(4 4) : lead-/halogen-free type (build-to-order ) ? development tools ? on-chip-debugger : (1) tcb87 typeb + LC87FBL08A (2) tcb87 typec (3 wire version) + LC87FBL08A
LC87FBL08A no.a1955-5/28 ? flash rom programming boards package programming boards qfp36 w87f24q vqlp32 (build-to-order ) ? flash rom programmer maker model supported version device single programmer af9709/af9709b/af9709c (including ando electric co., ltd. models) rev 03.28 or later 87f008su af9723/af9723b(main body) (including ando electric co., ltd. models) - - flash support group, inc. (fsg) gang programmer af9833(unit) (including ando electric co., ltd. models) - - af9101/af9103(main body) (fsg models) flash support group, inc. (fsg) + sanyo (note 1) in-circuit programmer sib87(inter face driver) (sanyo model) (note 2) - single/gang programmer skk / skk type b / skk type c (sanyofws) sanyo in-circuit/gang programmer skk-dbg type b / skk-dbg type c (sanyofws) application version 1.06 or later chip data version 2.34 or later lc87fbl08 for information about af-series: flash support group, inc. tel: +81-53-459-1050 e-mail: sales@j-fsg.co.jp note1: on-board-programmer from fsg (af9101/af9103) and serial interface driver from sanyo (sib87) together can give a pc-less, standalone on-board-programming capabilities. note2: it needs a special programming devices and applications depending on the use of programming environment. please ask fsg or sanyo for the information.
LC87FBL08A no.a1955-6/28 package dimensions unit : mm (typ) 3162c package dimensions unit : mm (typ) 3331 0.1 1.7max 0.3 0.65 (0.9) (1.5) sanyo : qfp36(7x7) 19 10 18 19 27 28 36 9.0 0.5 7.0 9.0 7.0 0.15 sanyo : vqlp32(4.0x4.0) 1 8 9 16 17 24 25 32 0.35 0.2 0.35 (0.6) 4.0 4.0 top view 0.85max 0.0nom 0.05 side view bottom view (0.6) 0.4
LC87FBL08A no.a1955-7/28 pin assignment sanyo: qfp36(7 7) ?lead-/halogen-free type? qfp36 name qfp36 name 1 p73/int3/t0in/an 11 19 p21/int4/t1in 2 res 20 p30/pwm4/int5/t1in 3 n.c. 21 p31/pwm5/int5/t1in 4 v ss 1 22 n.c. 5 cf1/xt1 23 v ss 2 6 cf2/xt2 24 p00/an0 7 v dd 1 25 p01/an1 8 p10 26 p02/an2 9 p11 27 p03/an3 10 p12 28 p04/an4 11 p13/so1/dbgp12 29 p05/an5/cko/dbgp00 12 p14/si1/sb1/dbgp11 30 p06/an6/t6o/dbgp01 13 p15/sck1/dbgp10 31 p07/t7o/dbgp02 14 n.c. 32 n.c. 15 n.c. 33 n.c. 16 p16/t1pwml 34 p70/int0/t0lcp/an8 17 p17/t1pwmh/buz 35 p71/int1/t0hcp/an9 18 p20/int4/t1in 36 p72/int2/t0in/an10 note: n.c. pins must be held open (disconnected). lc87fbl08 a top view p03/an3 p02/an2 p01/an1 p00/an0 v ss 2 n.c. p31/pwm5/int5/t1in p30/pwm4/int5/t1in p21/int4/t1in p73/int3/t0in/an11 res n.c. v ss 1 cf1/xt1 cf2/xt2 v dd 1 p10 p11 1 2 3 4 5 6 7 8 9 27 26 25 24 23 22 21 20 19 p04/an4 p05/an5/cko/dbgp00 p06/an6/t6o/dbgp01 p07/t7o/dbgp02 n.c. n.c. p70/int0/t0lcp/an8 p71/int1/t0hcp/an9 p72/int2/t0in/an10 18 17 16 15 14 13 12 11 10 p20/int4/t1in p17/t1pwmh/buz p16/t1pwml n.c. n.c. p15/sck1/dgbp10 p14/si1/sb1/dbgp11 p13/so1/dbgp12 p12 28 29 30 31 32 33 34 35 36
LC87FBL08A no.a1955-8/28 sanyo: vqlp32(4 4) ?lead-/halogen-free type? (build-to-order ) vqlp32 name vqlp32 name 1 res 17 p21/int4/t1in 2 n.c. 18 p30/pwm4/int5/t1in 3 v ss 1 19 p31/pwm5/int5/t1in 4 cf1/xt1 20 v ss 2 5 cf2/xt2 21 p00/an0 6 v dd 1 22 p01/an1 7 p10 23 p02/an2 8 p11 24 p03/an3 9 p12 25 p04/an4 10 p13/so1/dbgp12 26 p05/an5/cko/dbgp00 11 p14/si1/sb1/dbgp11 27 p06/an6/t6o/dbgp01 12 p15/sck1/dbgp10 28 p07/t7o/dbgp02 13 p16/t1pwml 29 p70/int0/t0lcp/an8 14 p17/t1pwmh/buz 30 p71/int1/t0hcp/an9 15 n.c. 31 p72/int2/t0in/an10 16 p20/int4/t1in 32 p73/int3/t0in/an11 note: n.c. pins must be held open (disconnected). res n.c. v ss 1 cf1/xt1 cf2/xt2 v dd 1 p10 p11 p03/an3 p02/an2 p01/an1 p00/an0 v ss 2 p31/pwm5/int5/t1in p30/pwm4/int5/t1in p21/int4/t1in 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 p04/an4 p05/an5/cko/dbgp00 p06/an6/t6o/dbgp01 p07/t7o/dbgp02 p70/int0/t0lcp/an8 p71/int1/t0hcp/an9 p72/int2/t0in/an10 p73/int3/t0in/an11 16 15 14 13 12 11 10 9 p20/int4/t1in n.c. p17/t1pwmh/buz p16/t1pwml p15/sck1/dbgp10 p14/si1/sb1/dbgp11 p13/so1/dbgp12 p12 25 26 27 28 29 30 31 32 lc87fbl08 a top view
LC87FBL08A no.a1955-9/28 system block diagram res interrupt control standby control ir pla bus interface port 0 port 1 sio1 timer 0 timer 1 port 7 adc alu flash rom pc acc b register c register psw rar ram stack pointer port 2 int4 base timer timer 6 int0-2 int3 (noise filter) timer 7 on-chip-debugger port 2 reset control reset circuit (lvd/por) wdt cf/ x'tal rc mrc src port 3 port 3 int5 pwm4 pwm5 clock generator
LC87FBL08A no.a1955-10/28 pin description pin name i/o description option v ss 1, v ss 2 - - power supply pin no v dd 1 - + power supply pin no port 0 p00 to p07 i/o ? 8-bit i/o port ? i/o specifiable in 4-bit units ? pull-up resistors can be turned on and off in 4-bit units. ? hold reset input ? port 0 interrupt input ? pin functions p05: system clock output p06: timer 6 toggle output p07: timer 7 toggle output p00(an0) to p06(an6): ad converter input p05(dbgp00) to p07(dbgp02): on-chip debugger 0 port yes port 1 p10 to p17 i/o ? 8-bit i/o port ? i/o specifiable in 1-bit units ? pull-up resistors can be turned on and off in 1-bit units. ? pin functions p13: sio1 data output p14: sio1 data input / bus i/o p15: sio1 clock i/o p16: timer 1pwml output p17: timer 1pwmh output / beeper output p15(dbgp10) to p13(dbgp12): on-chip-debugger 1 port yes port 2 p20 to p21 i/o ? 2-bit i/o port ? i/o specifiable in 1-bit units ? pull-up resistors can be turned on and off in 1-bit units. ? pin functions p20 to p21: int4 input / hold reset input / timer 1 event input / timer 0l capture input / timer 0h capture input interrupt acknowledge types rising falling rising & falling h level l level int4 enable enable enable disable disable yes port 3 ? 2-bit i/o port ? i/o specifiable in 1 bit units ? pull-up resistors can be turned on and off in 1 bit units. ? pin functions p30: pwm4 output p31: pwm5 output p30 to p31: int5 input/hold reset input / time r 1 event input / timer 0l capture input / timer 0h capture input interrupt acknowledge types rising falling rising & falling h level l level int5 enable enable enable disable disable p30 to p31 i/o yes continued on next page.
LC87FBL08A no.a1955-11/28 continued from preceding page. pin name i/o description option port 7 ? 4-bit i/o port ? i/o specifiable in 1 bit units ? pull-up resistors can be turned on and off in 1 bit units. ? pin functions p70: int0 input / hold reset input / timer 0l capture input p71: int1 input / hold reset input / timer 0h capture input p72: int2 input / hold reset input / time r 0 event input / timer 0l capture input p73: int3 input (with noise filter) / time r 0 event input / timer 0h capture input p70(an8) to p73(an11): ad converter input interrupt acknowledge types rising falling rising & falling h level l level int0 int1 int2 int3 enable enable enable enable enable enable enable enable disable disable enable enable enable enable disable disable enable enable disable disable p70 to p73 i/o no res i/o external reset input / internal reset output no cf1/xt1 i ? ceramic resonator or 32.768khz crystal oscillator input pin ? pin function general-purpose input port no cf2/xt2 i/o ? ceramic resonator or 32.768khz crystal oscillator output pin ? pin function general-purpose i/o port no port output types the table below lists the types of port outputs and the presence/absence of a pull-up resistor. data can be read into any input port even if it is in the output mode. port name option selected in units of option type output type pull-up resistor 1 cmos programmable (note 1) p00 to p07 1 bit 2 nch-open drain no 1 cmos programmable p10 to p17 1 bit 2 nch-open drain programmable 1 cmos programmable p20 to p21 1 bit 2 nch-open drain programmable 1 cmos programmable p30 to p31 1 bit 2 nch-open drain programmable p70 - no nch-open drain programmable p71 to p73 - no cmos programmable cf2/xt2 - no ceramic resonator/32.768khz crystal resonator output nch-open drain (n-channel open drain when set to general-purpose output port) no note 1: the control of the presence or absence of the programmable pull-up resistors for port 0 and the switching between low-and high-impedance pull-up connection is ex ercised in nibble (4-bit) units (p00 to 03 or p04 to 07).
LC87FBL08A no.a1955-12/28 user option table option name option to be applied on mask version *1 flash-rom version option selected in units of option selection cmos p00 to p07 { { 1 bit nch-open drain cmos p10 to p17 { { 1 bit nch-open drain cmos p20 to p21 { { 1 bit nch-open drain cmos port output type p30 to p31 { { 1 bit nch-open drain 00000h program start address - *2 { - 01e00h enable:use detect function { { - disable:not used low-voltage detection reset function detect level { { - 3-level power-on reset function power-on reset level { { - 4-level * 1: mask option selection - no change possible after mask is completed. * 2: program start address of the mask version is 00000h. recommended unused pin connections recommended unused pin connections port name board software p00 to p07 open output low p10 to p17 open output low p20 to p21 open output low p30 to p31 open output low p70 to p73 open output low cf1/xt1 pulled low with a 100k resistor or less general-purpose input port cf2/xt2 pulled low with a 100k resistor or less general-purpose input port on-chip debugger pin connection requirements for the treatment of the on-chip debugger pins, refer to the separately available documents entitled "rd87 on-chip debugger installation manual". power pin treatment recommendations (v dd 1, v ss 1) connect bypass capacitors that meet the following conditions between the v dd 1 and v ss 1 pins: ? connect among the v dd 1 and v ss 1 pins and bypass capacitors c1 and c2 with the shortest possible heavy lead wires, making sure that the impedances between the both pins and the bypass capacitors are as possible (l1=l1? , l2=l2?). ? connect a large-capacity cap acitor c1 and a small-capacity capacitor c2 in parallel. the capacitance of c2 should approximately 0.1 f. note : be sure to electrically short-circuit between the v ss 1 and v ss 2 pins. v ss 1 v dd 1 l1? l2? l1 l2 c1 c2
LC87FBL08A no.a1955-13/28 absolute maximum ratings at ta = 25 c, v ss 1 = v ss 2 = 0v specification parameter symbol pin/remarks conditions v dd [v] min typ max unit maximum supply voltage v dd max v dd 1 -0.3 +6.5 input voltage v i cf1 -0.3 v dd +0.3 input/output voltage v io ports 0, 1, 2, 3, 7, cf2, res -0.3 v dd +0.3 v ioph(1) ports 0, 1, 2, 3 cmos output select per 1 applicable pin -10 peak output current ioph(2) p71 to p73 per 1 applicable pin -5 mean output current (note 1-1) iomh(1) ports 0, 1, 2, 3 p71 to p73 cmos output select per 1 applicable pin -7.5 high level output current total output current ioah(1) ports 0, 1, 2, 3, p71 to p73 total of all applicable pins -25 iopl(1) p02 to p07, ports 1, 2, 3 per 1 applicable pin 20 iopl(2) p00, p01 per 1 applicable pin 30 peak output current iopl(3) ports 7, cf2 per 1 applicable pin 10 ioml(1) p02 to p07, ports 1, 2, 3 per 1 applicable pin 15 ioml(2) p00, p01 per 1 applicable pin 20 mean output current (note 1-1) ioml(3) ports 7, cf2 per 1 applicable pin 7.5 ioal(1) ports 0, 1, ports 2, 3, cf2 total of all applicable pins 70 low level output current total output current ioal(2) ports 7 total of all applicable pins 15 ma pd max(1) ta=-40 to +85 c package only 120 power dissipation pd max(2) qfp36 (7 7) ta=-40 to +85 c package with thermal resistance board (note 1-2) 275 mw operating ambient temperature topr -40 +85 storage ambient temperature tstg -55 +125 c note 1-1: the mean output current is a mean value measured over 100ms. note 1-2: semi standards ther mal resistance board (size: 76.1 114.3 1.6tmm, glass epoxy) is used.
LC87FBL08A no.a1955-14/28 allowable operating conditions at ta = -40 c to +85 c, v ss 1 = v ss 2 = 0v specification parameter symbol pin/remarks conditions v dd [v] min typ max unit operating supply voltage v dd v dd 1 0.245 s tcyc 200 s 2.7 5.5 memory sustaining supply voltage vhd v dd 1 ram and register contents sustained in hold mode. 1.6 v ih (1) ports 1, 2, 3, 7 2.7 to 5.5 0.3v dd +0.7 v dd v ih (2) ports 0 2.7 to 5.5 0.3v dd +0.7 v dd high level input voltage v ih (3) cf1, cf2, res 2.7 to 5.5 0.75v dd v dd 4.0 to 5.5 v ss 0.1v dd +0.4 v il (1) ports 1, 2, 3, 7 2.7 to 4.0 v ss 0.2v dd 4.0 to 5.5 v ss 0.15v dd +0.4 v il (2) ports 0 2.7 to 4.0 v ss 0.2v dd low level input voltage v il (3) cf1, cf2, res 2.7 to 5.5 v ss 0.25v dd v i oh (1) 4.5 to 5.5 -1.0 i oh (2) ports 0, 1, 2, p71 to p73 per 1 applicable pin 2.7 to 4.5 -0.35 i oh (3) 4.5 to 5.5 -6.0 i oh (4) ports 3, p05 (system clock output function used) per 1 applicable pin 2.7 to 4.5 -1.4 i oh (1) 4.5 to 5.5 -25 high level output current i oh (2) ports 0, 1, 2, 3, 7 total of all applicable pins 2.7 to 4.5 -11.2 i ol (1) 4.5 to 5.5 10 i ol (2) ports 0, 1, 2, 3 per 1 applicable pin 2.7 to 4.5 1.4 i ol (3) ports 7, cf2 per 1 applicable pin 2.7 to 5.5 1.4 i ol (4) 4.5 to 5.5 25 i ol (5) p00, p01 per 1 applicable pin 2.7 to 4.5 4 i ol (1) 4.5 to 5.5 70 i ol (2) ports 0, 1, 2, 3, cf2 total of all applicable pins 2.7 to 4.5 34.6 low level output current i ol (3) ports 7 total of all applicable pins 2.7 to 5.5 5.6 ma instruction cycle time (note 2-1) tcyc 2.7 to 5.5 0.245 200 s ? cf2 pin open ? system clock frequency division ratio=1/1 ? external system clock duty=50 5% 2.7 to 5.5 0.1 12 external system clock frequency fexcf cf1 ? cf2 pin open ? system clock frequency division ratio=1/2 ? external system clock duty=50 5% 3.0 to 5.5 0.2 24.4 mhz note 2-1: relationship between tcyc and oscillation frequency is 3/fmcf at a division ratio of 1/1 and 6/fmcf at a division ratio of 1/2. continued on next page.
LC87FBL08A no.a1955-15/28 continued from preceding page. specification parameter symbol pin/remarks conditions v dd [v] min typ max unit fmcf(1) cf1, cf2 12mhz ceramic oscillation. see fig. 1. 2.7 to 5.5 12 fmcf(2) cf1, cf2 10mhz ceramic oscillation. see fig. 1. 2.7 to 5.5 10 4mhz ceramic oscillation. cf oscillation normal am plifier size selected. (cflamp=0) see fig. 1. 2.7 to 5.5 4 fmcf(3) cf1, cf2 4mhz ceramic oscillation. cf oscillation low amplifier size selected. (cflamp=1) see fig. 1. 2.7 to 5.5 4 fmmrc(1) frequency variable rc oscillation. (note 2-3) 2.7 to 5.5 7.76 8.0 8.24 fmmrc(2) frequency variable rc oscillation. ? ta=-10 to +85 c (note 2-3) 2.7 to 5.5 7.80 8.0 8.20 fmrc internal medium-speed rc oscillation 2.7 to 5.5 0.5 1.0 2.0 mhz fmsrc internal low-speed rc oscillation 2.7 to 5.5 50 100 200 oscillation frequency range (note 2-2) fsx?tal xt1, xt2 32.768khz crystal oscillation see fig. 1. 2.7 to 5.5 32.768 khz oscillation stabilization time tmsmrc when frequency variable rc oscillation state is switched from stopped to enabled. see fig. 3. 2.7 to 5.5 100 s note 2-2: see tables 1 and 2 for the oscillation constants. note 2-3: when switching the system clock, allow an oscillation stabilization time of 100 s or longer after the frequency variable rc oscillator circuit transmits from th e "oscillation stopped" to "oscillation enabled" state.
LC87FBL08A no.a1955-16/28 electrical characteristics at ta = -40 c to +85 c, v ss 1 = v ss 2 = 0v specification parameter symbol pin/remarks conditions v dd [v] min typ max unit i ih (1) ports 0, 1, 2, 3, ports 7, res output disabled pull-up resistor off v in =v dd (including output tr's off leakage current) 2.7 to 5.5 1 i ih (2) cf1, cf2 input port selected v in =v dd 2.7 to 5.5 1 high level input current iih(3) cf1 reset state v in =v dd 2.7 to 5.5 15 i il (1) ports 0, 1, 2, 3, ports 7, res output disabled pull-up resistor off v in =v ss (including output tr's off leakage current) 2.7 to 5.5 -1 low level input current i il (2) cf1, cf2 input port selected v in =v ss 2.7 to 5.5 -1 a v oh (1) i oh =-1ma 4.5 to 5.5 v dd -1 v oh (2) ports 0, 1, 2, p71 to p73 i oh =-0.35ma 2.7 to 5.5 v dd -0.4 v oh (3) i oh =-6ma 4.5 to 5.5 v dd -1 high level output voltage v oh (4) ports 3, p05 (system clock output function used) i oh =-1.4ma 2.7 to 5.5 v dd -0.4 v ol (1) i ol =10ma 4.5 to 5.5 1.5 v ol (2) ports 0, 1, 2, 3 i ol =1.4ma 2.7 to 5.5 0.4 v ol (3) ports7, cf2 i ol =1.4ma 2.7 to 5.5 0.4 v ol (4) i ol =25ma 4.5 to 5.5 1.5 low level output voltage v ol (5) p00, p01 i ol =4ma 2.7 to 5.5 0.4 v rpu(1) 4.5 to 5.5 15 35 80 rpu(2) ports 0, 1, 2, 3, ports 7 v oh =0.9v dd when port 0 selected low-impedance pull-up. 2.7 to 4.5 18 50 150 pull-up resistance rpu(3) port 0 v oh =0.9v dd when port 0 selected high-impedance pull-up. 2.7 to 5.5 100 200 300 k hysteresis voltage vhys ports 1, 2, 3, 7, res 2.7 to 5.5 0.1v dd v pin capacitance cp all pins for pins other than that under test: v in =v ss f=1mhz ta=25 c 2.7 to 5.5 10 pf
LC87FBL08A no.a1955-17/28 sio1 serial i/o characteristics at ta = -40 c to +85 c, v ss 1 = v ss 2 = 0v (note 4) specification parameter symbol pin/ remarks conditions v dd [v] min typ max unit frequency tsck(3) 2 low level pulse width tsckl(3) 1 input clock high level pulse width tsckh(3) sck1(p15) ? see fig. 5. 2.7 to 5.5 1 frequency tsck(4) 2 tcyc low level pulse width tsckl(4) 1/2 serial clock output clock high level pulse width tsckh(4) sck1(p15) ? cmos output selected ? see fig. 5. 2.7 to 5.5 1/2 tsck data setup time tsdi(2) (1/3)tcyc +0.01 serial input data hold time thdi(2) sb1(p14), si1(p14) ? must be specified with respect to rising edge of sioclk. ? see fig. 5. 2.7 to 5.5 0.01 serial output output delay time tdd0(4) so1(p13), sb1(p14) ? must be specified with respect to falling edge of sioclk. ? must be specified as the time to the beginning of output state change in open drain output mode. ? see fig. 5. 2.7 to 5.5 (1/2)tcyc +0.05 s note 4: these specifications are theoretical values. add margin depending on its use. pulse input conditions at ta = -40 c to +85 c, v ss 1 = v ss 2 = 0v specification parameter symbol pin/remarks conditions v dd [v] min typ max unit tpih(1) tpil(1) int0(p70), int1(p71), int2(p72), int4(p20 to p21), int5(p30 to p31) ? interrupt source flag can be set. ? event inputs for timer 0 or 1 are enabled. 2.7 to 5.5 1 tpih(2) tpil(2) int3(p73) when noise filter time constant is 1/1 ? interrupt source flag can be set. ? event inputs for timer 0 are enabled. 2.7 to 5.5 2 tpih(3) tpil(3) int3(p73) when noise filter time constant is 1/32 ? interrupt source flag can be set. ? event inputs for timer 0 are nabled. 2.7 to 5.5 64 tpih(4) tpil(4) int3(p73) when noise filter time constant is 1/128 ? interrupt source flag can be set. ? event inputs for timer 0 are enabled. 2.7 to 5.5 256 tcyc high/low level pulse width tpil(5) res ? resetting is enabled. 2.7 to 5.5 200 s
LC87FBL08A no.a1955-18/28 ad converter characteristics at v ss 1 = v ss 2 = 0v <12bits ad converter mode/ta = -40 c to +85 c > specification parameter symbol pin/remarks conditions v dd [v] min typ max unit resolution n 2.7 to 5.5 12 bit 3.0 to 5.5 16 absolute accuracy et (note 6-1) 2.7 to 5.5 20 lsb 4.0 to 5.5 32 115 3.0 to 5.5 64 115 conversion time tcad ? see conversion time calculation formulas. (note 6-2) 2.7 to 5.5 134 215 s analog input voltage range vain 2.7 to 5.5 v ss v dd v iainh vain=v dd 2.7 to 5.5 1 analog port input current iainl an0(p00) to an6(p06), an8(p70) to an11(p73) vain=v ss 2.7 to 5.5 -1 a <8bits ad converter mode/ta = -40 c to +85 c > specification parameter symbol pin/remarks conditions v dd [v] min typ max unit resolution n 2.7 to 5.5 8 bit absolute accuracy et (note 6-1) 2.7 to 5.5 1.5 lsb 4.0 to 5.5 20 90 3.0 to 5.5 40 90 conversion time tcad ? see conversion time calculation formulas. (note 6-2) 2.7 to 5.5 80 135 s analog input voltage range vain 2.7 to 5.5 v ss v dd v iainh vain=v dd 2.7 to 5.5 1 analog port input current iainl an0(p00) to an6(p06), an8(p70) to an11(p73) vain=v ss 2.7 to 5.5 -1 a conversion time calculation formulas: 12bits ad converter mode: tcad(conversion time) = ((52/(ad division ratio))+2) (1/3) tcyc 8bits ad converter mode: tcad(conversion time) = ((32/(ad division ratio))+2) (1/3) tcyc ad conversion time (tcad) external oscillation (fmcf) operating supply voltage range (v dd ) system division ratio (sysdiv) cycle time (tcyc) ad division ratio (addiv) 12bit ad 8bit ad 4.0v to 5.5v 1/1 250ns 1/8 34.8 s 21.5 s 3.0v to 5.5v 1/1 250ns 1/16 69.5 s 42.8 s cf-12mhz 2.7v to 5.5v 1/1 250ns 1/32 138.8 s 85.5 s 4.0v to 5.5v 1/1 375ns 1/8 52.25 s 32.25 s 3.0v to 5.5v 1/1 375ns 1/16 104.25 s 64.25 s cf-8mhz 2.7v to 5.5v 1/1 375ns 1/32 208.25 s 128.25 s 3.0v to 5.5v 1/1 750ns 1/8 104.5 s 64.5 s cf-4mhz 2.7v to 5.5v 1/1 750ns 1/16 208.5 s 128.5 s note 6-1: the quantization error (1/2lsb ) must be excluded from the absolute accuracy. the absolute accuracy must be measured in the microcontroller's state in which no i/o operations occur at the pins adjacent to the analog input channel. note 6-2: the conversion time refers to the period from the time an instruction for starting a conversion process till the time the conversion results register(s) are loaded with a complete digital conversion value corresponding to the analog input value. the conversion time is 2 times the normal-time conversion time when: ? the first ad conversion is performed in the 12 -bit ad conversion mode after a system reset. ? the first ad conversion is performed after the ad conversion mode is switched from 8-bit to 12-bit conversion mode.
LC87FBL08A no.a1955-19/28 power-on reset (por) characteristics at ta = -40 c to +85 c, v ss 1 = v ss 2 = 0v specification parameter symbol pin/remarks conditions option selected voltage min typ max unit 2.57v 2.45 2.57 2.69 2.87v 2.75 2.87 2.99 3.86v 3.73 3.86 3.99 por release voltage porrl ? select from option. (note 7-1) 4.35v 4.21 4.35 4.49 detection voltage unknown state pouks ? see fig. 7. (note 7-2) 0.7 0.95 v power supply rise time poris ? power supply rise time from 0v to 1.6v. 100 ms note7-1: the por release level can be selected out of 4 levels only when the lvd reset function is disabled. note7-2: por is in an unknown state before transistors start operation. low voltage detection reset (lvd) characteristics at ta = -40 c to +85 c, v ss 1 = v ss 2 = 0v specification parameter symbol pin/remarks conditions option selected voltage min typ max unit 2.81v 2.71 2.81 2.91 3.79v 3.67 3.79 3.91 lvd reset voltage (note 8-2) lvdet 4.28v 4.15 4.28 4.41 v 2.81v 60 3.79v 65 lvd hysteresys width lvhys ? select from option. (note 8-1) (note 8-3) ? see fig. 8. 4.28v 65 mv detection voltage unknown state lvuks ? see fig. 8. (note 8-4) 0.7 0.95 v low voltage detection minimum width (reply sensitivity) tlvdw ? lvdet-0.5v ? see fig. 9. 0.2 ms note8-1: the lvd reset level can be selected out of 3 levels only when the lvd reset function is enabled. note8-2: lvd reset voltage specification values do not include hysteresis voltage. note8-3: lvd reset voltage may exceed its specification values when port output state changes and/or when a large current flows through port. note8-4: lvd is in an unknown state before transistors start operation.
LC87FBL08A no.a1955-20/28 consumption current characteristics at ta = -40 c to +85 c, v ss 1 = v ss 2 = 0v specification parameter symbol pin/ remarks conditions v dd [v] min typ max unit 2.7 to 5.5 4.8 8.7 iddop(1) ? fmcf=12mhz ceramic oscillation mode ? system clock set to 12mhz side ? internal low speed and medium speed rc oscillation stopped. ? frequency variable rc oscillation stopped. ? 1/1 frequency division ratio 2.7 to 3.6 3.0 5.0 3.0 to 5.5 5.0 9.6 iddop(2) ? cf1=24mhz external clock ? system clock set to cf1 side ? internal low speed and medium speed rc oscillation stopped. ? frequency variable rc oscillation stopped. ? 1/2 frequency division ratio 3.0 to 3.6 3.2 6.0 2.7 to 5.5 4.1 7.8 iddop(3) ? fmcf=10mhz ceramic oscillation mode ? system clock set to 10mhz side ? internal low speed and medium speed rc oscillation stopped. ? frequency variable rc oscillation stopped. ? 1/1 frequency division ratio 2.7 to 3.6 2.6 4.9 2.7 to 5.5 2.2 5.1 iddop(4) ? fmcf=4mhz ceramic oscillation mode ? system clock set to 4mhz side ? internal low speed and medium speed rc oscillation stopped. ? frequency variable rc oscillation stopped. ? 1/1 frequency division ratio 2.7 to 3.6 1.5 2.7 2.7 to 5.5 0.95 2.4 iddop(5) ? cf oscillation low amplifier size selected. (cflamp=1) ? fmcf=4mhz ceramic oscillation mode ? system clock set to 4mhz side ? internal low speed and medium speed rc oscillation stopped. ? frequency variable rc oscillation stopped. ? 1/4 frequency division ratio 2.7 to 3.6 0.50 1.1 2.7 to 5.5 0.42 1.4 iddop(6) ? fsx?tal=32.768khz crystal oscillation mode ? internal low speed rc oscillation stopped. ? system clock set to internal medium speed rc oscillation. ? frequency variable rc oscillation stopped. ? 1/2 frequency division ratio 2.7 to 3.6 0.25 0.76 2.7 to 5.5 3.2 5.4 iddop(7) ? fsx?tal=32.768khz crystal oscillation mode ? internal low speed and medium speed rc oscillation stopped. ? system clock set to 8mhz with frequency variable rc oscillation ? 1/1 frequency division ratio 2.7 to 3.6 2.3 4.2 ma 2.7 to 5.5 55 169 iddop(8) ? external fsx?tal and fmcf oscillation stopped. ? system clock set to internal low speed rc oscillation. ? internal medium speed rc oscillation sopped. ? frequency variable rc oscillation stopped. ? 1/1 frequency division ratio 2.7 to 3.6 39 109 5.0 55 136 normal mode consumption current (note 9-1) (note 9-2) iddop(9) v dd 1 ? external fsx?tal and fmcf oscillation stopped. ? system clock set to internal low speed rc oscillation. ? internal medium speed rc oscillation stopped. ? frequency variable rc oscillation stopped. ? 1/1 frequency division ratio ? ta=-10 to +50 c 3.3 39 103 a note9-1: values of the consumption current do not include current that flows into the output transistors and internal pull-up resistors. note9-2: the consumption current values do not include operational current of lvd function if not specified. continued on next page.
LC87FBL08A no.a1955-21/28 continued from preceding page. specification parameter symbol pin/ remarks conditions v dd [v] min typ max unit 2.7 to 5.5 28 89 iddop(10) ? fsx?tal=32.768khz crystal oscillation mode ? system clock set to 32.768khz side ? internal low speed and medium speed rc oscillation stopped. ? frequency variable rc oscillation stopped. ? 1/2 frequency division ratio 2.7 to 3.6 11 38 5.0 28 78 normal mode consumption current (note 9-1) (note 9-2) iddop(11) ? fsx?tal=32.768khz crystal oscillation mode ? system clock set to 32.768khz side ? internal low speed and medium speed rc oscillation stopped. ? frequency variable rc oscillation stopped. ? 1/2 frequency division ratio ? ta=-10 to +50 c 3.3 11 29 a 2.7 to 5.5 2.4 4.5 iddhalt(1) ? halt mode ? fmcf=12mhz ceramic oscillation mode ? system clock set to 12mhz side ? internal low speed and medium speed rc oscillation stopped. ? frequency variable rc oscillation stopped. ? 1/1 frequency division ratio 2.7 to 3.6 1.3 2.2 3.0 to 5.5 2.7 5.3 iddhalt(2) ? halt mode ? cf1=24mhz external clock ? system clock set to cf1 side ? internal low speed and medium speed rc oscillation stopped. ? frequency variable rc oscillation stopped. ? 1/2 frequency division ratio 3.0 to 3.6 1.6 2.9 2.7 to 5.5 2.0 4.1 iddhalt(3) ? halt mode ? fmcf=10mhz ceramic oscillation mode ? system clock set to 10mhz side ? internal low speed and medium speed rc oscillation stopped. ? frequency variable rc oscillation stopped. ? 1/1 frequency division ratio 2.7 to 3.6 1.1 2.1 2.7 to 5.5 1.2 3.3 iddhalt(4) ? halt mode ? fmcf=4mhz ceramic oscillation mode ? system clock set to 4mhz side ? internal low speed and medium speed rc oscillation stopped. ? frequency variable rc oscillation stopped. ? 1/1 frequency division ratio 2.7 to 3.6 0.50 1.2 2.7 to 5.5 0.70 1.8 iddhalt(5) ? halt mode ? cf oscillation low amplifier size selected. (cflamp=1) ? fmcf=4mhz ceramic oscillation mode ? system clock set to 4mhz side ? internal low speed and medium speed rc oscillation stopped. ? frequency variable rc oscillation stopped. ? 1/4 frequency division ratio 2.7 to 3.6 0.30 0.68 2.7 to 5.5 0.30 0.90 halt mode consumption current (note 9-1) (note 9-2) iddhalt(6) v dd 1 ? halt mode ? fsx?tal=32.768khz crystal oscillation mode ? internal low speed rc oscillation stopped. ? system clock set to internal medium speed rc oscillation ? frequency variable rc oscillation stopped. ? 1/2 frequency division ratio 2.7 to 3.6 0.20 0.44 ma note9-1: values of the consumption current do not include current that flows into the output transistors and internal pull-up resistors. note9-2: the consumption current values do not include operational current of lvd function if not specified. continued on next page.
LC87FBL08A no.a1955-22/28 continued from preceding page. specification parameter symbol pin/ remarks conditions v dd [v] min typ max unit 2.7 to 5.5 1.3 2.3 iddhalt(7) ? halt mode ? fsx?tal=32.768khz crystal oscillation mode ? internal low speed and medium speed rc oscillation stopped. ? system clock set to 8mhz with frequency variable rc oscillation ? 1/1 frequency division ratio 2.7 to 3.6 0.90 1.5 ma 2.7 to 5.5 18 68 iddhalt(8) ? halt mode ? external fsx?tal and fmcf oscillation stopped. ? system clock set to internal low speed rc oscillation. ? internal medium speed rc oscillation stopped. ? frequency variable rc oscillation stopped. ? 1/1 frequency division ratio 2.7 to 3.6 11 35 5.0 18 46 iddhalt(9) ? halt mode ? external fsx?tal and fmcf oscillation stopped. ? system clock set to internal low speed rc oscillation. ? internal medium speed rc oscillation stopped. ? frequency variable rc oscillation stopped. ? 1/1 frequency division ratio ? ta=-10 to +50 c 3.3 11 27 2.7 to 5.5 20 85 iddhalt(10) ? halt mode ? fsx?tal=32.768khz crystal oscillation mode ? system clock set to 32.768khz side ? internal low speed and medium speed rc oscillation stopped. ? frequency variable rc oscillation stopped. ? 1/2 frequency division ratio 2.7 to 3.6 5.6 30 5.0 20 51 halt mode consumption current (note 9-1) (note 9-2) iddhalt(11) ? halt mode ? fsx?tal=32.768khz crystal oscillation mode ? system clock set to 32.768khz side ? internal low speed and medium speed rc oscillation stopped. ? frequency variable rc oscillation stopped. ? 1/2 frequency division ratio ? ta=-10 to +50 c 3.3 5.6 17 2.7 to 5.5 0.012 23 iddhold(1) hold mode ? cf1=v dd or open (external clock mode) 2.7 to 3.6 0.008 11 5.0 0.012 1.2 iddhold(2) hold mode ? cf1=v dd or open (external clock mode) ? ta=-10 to +50 c 3.3 0.008 0.59 2.7 to 5.5 2.0 26 iddhold(3) hold mode ? cf1=v dd or open (external clock mode) ? lvd option selected 2.7 to 3.6 1.6 13 5.0 2.0 3.8 hold mode consumption current (note 9-1) (note 9-2) iddhold(4) hold mode ? cf1=v dd or open (external clock mode) ? ta=-10 to +50 c ? lvd option selected 3.3 1.6 2.8 2.7 to 5.5 16 70 iddhold(5) timer hold mode ? fsx?tal=32.768 khz crystal oscillation mode 2.7 to 3.6 4.2 25 5.0 16 42 timer hold mode consumption current (note 9-1) (note 9-2) iddhold(6) v dd 1 timer hold mode ? fsx?tal=32.768khz crystal oscillation mode ? ta=-10 to +50 c 3.3 4.2 11 a note9-1: values of the consumption current do not include current that flows into the output transistors and internal pull-up resistors. note9-2: the consumption current values do not include operational current of lvd function if not specified.
LC87FBL08A no.a1955-23/28 f-rom programming characteristics at ta = +10 c to +55 c, v ss 1 = v ss 2 = 0v specification parameter symbol pin/remarks conditions v dd [v] min typ max unit onboard programming current iddfw(1) v dd 1 ? only current of the flash block. 2.7 to 5.5 5 10 ma tfw(1) ? erasing time 20 30 ms programming time tfw(2) ? programming time 2.7 to 5.5 40 60 s characteristics of a sample main system clock oscillation circuit given below are the characteristics of a sample main syst em clock oscillation circuit that are measured using a sanyo-designated oscillation characteristics evaluation board and external components with circuit constant values with which the oscillator vendor confirmed normal and stable oscillation. table 1 characteristics of a sample main system clock oscillator circuit with a ceramic oscillator ? cf oscillation normal amplifier size selected (cflamp=0) ? murata circuit constant oscillation stabilization time nominal frequency type oscillator name c1 [pf] c2 [pf] rf [ ] rd [ ] operating voltage range [v] typ [ms] max [ms] remarks 12mhz smd cstce12m0g52-r0 (10) (10) open 680 2.7 to 5.5 0.02 0.3 smd cstce10m0g52-r0 (10) (10) open 680 2.7 to 5.5 0.02 0.3 10mhz lead cstls10m0g53-b0 (15) (15) open 680 2.7 to 5.5 0.02 0.3 smd cstce8m00g52-r0 (10) (10) open 1.0k 2.7 to 5.5 0.02 0.3 8mhz lead cstls8m00g53-b0 (15) (15) open 1.0k 2.7 to 5.5 0.02 0.3 smd cstcr6m00g53-r0 (15) (15) open 1.5k 2.7 to 5.5 0.02 0.3 6mhz lead cstls6m00g53-b0 (15) (15) open 1.5k 2.7 to 5.5 0.02 0.3 smd cstcr4m00g53-r0 (15) (15) open 1.5k 2.7 to 5.5 0.03 0.45 4mhz lead cstls4m00g53-b0 (15) (15) open 1.5k 2.7 to 5.5 0.02 0.3 internal c1, c2 ? cf oscillation low amplifier size selected (cflamp=1) ? murata circuit constant oscillation stabilization time nominal frequency type oscillator name c1 [pf] c2 [pf] rf [ ] rd [ ] operating voltage range [v] typ [ms] max [ms] remarks 12mhz smd cstce12m0g52-r0 (10) (10) open 470 3.9 to 5.5 0.04 0.6 smd cstce10m0g52-r0 (10) (10) open 470 2.9 to 5.5 0.03 0.45 cstls10m0g53-b0 (15) (15) open 470 3.6 to 5.5 0.03 0.45 10mhz lead cstls10m0g53095-b0 (15) (15) open 470 2.7 to 5.5 0.02 0.3 smd cstce8m00g52-r0 (10) (10) open 680 2.7 to 5.5 0.03 0.45 cstls8m00g53-b0 (15) (15) open 680 3.0 to 5.5 0.03 0.45 8mhz lead cstls8m00g53093-b0 (15) (15) open 680 2.7 to 5.5 0.02 0.3 smd cstcr6m00g53-r0 (15) (15) open 1.0k 2.7 to 5.5 0.03 0.45 cstls6m00g53-b0 (15) (15) o pen 1.0k 2.8 to 5.5 0.03 0.45 6mhz lead cstls6m00g53093-b0 (15) (15) open 1.0k 2.7 to 5.5 0.02 0.3 smd cstcr4m00g53-r0 (15) (15) open 1.0k 2.7 to 5.5 0.04 0.6 4mhz lead cstls4m00g53-b0 (15) (15) open 1.0k 2.7 to 5.5 0.02 0.3 internal c1, c2 the oscillation stabilization time refers to the time interval that is required for the oscillation to get stabilized in follwing cases (see figure 3). ? the time interval that is required for the oscillation to get stabilized after the instruction for starting the mainclock oscillation circuit is executed. ? the time interval that is required for the oscillation to ge t stabilized after the hold mode is reset and oscillation is started. ? the time interval that is required for the oscillation to ge t stabilized after the x?tal hold mode, under the state which the main clock oscillation is enabled, is reset and oscillation is started.
LC87FBL08A no.a1955-24/28 characteristics of a sample subs ystem clock oscillator circuit given below are the characteristics of a sample subsystem clock oscillation circuit that are measured using a sanyo- designated oscillation characteristics evaluation board and exte rnal components with circuit constant values with which the oscillator vendor confirmed normal and stable oscillation. table 2 characteristics of a sample subsystem cl ock oscillator circuit with a crystal oscillator ? epson toyocom circuit constant oscillation stabilization time nominal frequency type oscillator name c1 [pf] c2 [pf] rf [ ] rd [ ] operating voltage range [v] typ [s] max [s] remarks 32.768khz smd mc-306 9 9 open 330k 2.7 to 5.5 1.4 4.0 applicable cl value = 7.0pf ? seiko instruments circuit constant oscillation stabilization time nominal frequency type oscillator name c1 [pf] c2 [pf] rf [ ] rd [ ] operating voltage range [v] typ [s] max [s] remarks 32.768khz smd ssp-t7-f 22 22 open 0 2.7 to 5.5 0.75 2.0 applicable cl value = 12.5pf the oscillation stabilization time refers to the time interval th at is required for the oscillation to get stabilized after v dd goes above the operating voltage lower limit (see figure 3). ? the time interval that is required for the oscillation to get stabilized after the instruction for starting the subclock oscillation circuit is executed. ? the time interval that is required for the oscillation to get stabilized after the hold mode, under the state which the subclock oscillation is enabled, is reset and oscillation is started. (notes on the implementation of the oscillator circuit) ? oscillation is influenced by the circuit pattern layout of printed circuit board. place the oscillation-related components as close to the cpu chip and to each other as possible with the shortest possible pattern length. ? keep the signal lines whose state changes suddenly or in which large current flows as far away from the oscillator circuit as possible and make sure that they do not cross one another. ? be sure to insert a current limiting resistor (rd) so that the oscillation amplitude never exceeds the input voltage level that is specified as the absolute maximum rating. ? the oscillator circuit constants shown above are sample characteristic values that ar e measured using the sanyo- designated oscillation evaluation board. since the accuracy of the oscillation frequency and other characteristics vary according to the board on which the ic is installed, it is recommended that the user consult the resonator vendor for oscillation evaluation of the ic on a user's production boar d when using the ic for applications that require high oscillation accuracy. for further information, contact your resonator vendor or sanyo semiconductor sales representative serving your locality. ? it must be noted, when replacing the flash rom version of a microcontroller with a mask rom version, that their operating voltage ranges may differ even when the oscillati on constant of the external oscillator is the same. figure 1 cf and xt oscillator circu it figure 2 ac timing measurement point 0.5v dd rf rd cf1/xt1 cf2/xt2 c2 cf/x?tal c1
LC87FBL08A no.a1955-25/28 reset time and oscillation stabilization time hold reset signal and oscillation stabilization time note: external oscillation circuit is selected. figure 3 oscillation stabilization times res v dd operating v dd lower limit 0v power supply internal medium speed rc oscillation reset time cf1/xt1 tmscf/tmsxtal operating mode unpredictable reset instruction execution instruction for enabling oscillation executed cf2/xt2 tmsmrc frequency variable rc oscillation cf1/xt1, cf2/xt2 (note) tmscf/tmsxtal tmsmrc frequency variable rc oscillation hold halt hold reset signal internal medium speed rc oscillation or low speed rc oscillation state instruction execution hold reset signal absent hold reset signal valid halt reset signal valid instruction for enabling oscillation executed
LC87FBL08A no.a1955-26/28 figure 4 reset circuit figure 5 serial i/o output waveforms figure 6 pulse input timing signal waveform c res v dd r res res note: external circuits for reset may vary depending on the usage of por and lvd. please refer to the user?s manual for more information. di0 di7 di2 di3 di4 di5 di6 do0 do7 do2 do3 do4 do5 do6 di1 do1 sioclk: datain: dataout: dataout : datain: sioclk: tsck tsckl tsckh thdi tsdi tddo tpil tpih
LC87FBL08A no.a1955-27/28 figure 7 waveform observed when only por is used (lvd not used) (reset pin: pull-up resistor r res only) ? the por function generates a reset only wh en power is turned on starting at the v ss level. ? no stable reset will be generated if power is turned on again when the power level does not go down to the v ss level as shown in (a). if such a case is an ticipated, use the lvd function together with the por function or implement an external reset circuit. ? a reset is generated only when the power level goes down to the v ss level as shown in (b) and power is turned on again after this condition continues for 100 s or longer. figure 8 waveform observed when both por and lvd functions are used (reset pin: pull-up resistor r res only) ? resets are generated both when power is tu rned on and when the power level lowers. ? a hysteresis width (lvhys) is provided to prevent the repetitions of reset releas e and entry cycles near the detection level. por release voltage ( porrl ) v dd res unknown-state ( pouks ) (a) (b) reset period reset period 100
LC87FBL08A no.a1955-28/28 figure 9 low voltage detection minimum width (example of momentary power loss/voltage variation waveform) ps this catalog provides information as of april, 2011. specifications and info rmation herein are subject to change without notice. v dd lvd reset voltage tlvdw v ss lvd release voltage lvdet-0.5v sanyo semiconductor co.,ltd. assumes no responsibil ity for equipment failures that result from using products at values that exceed, even momentarily, rated v alues (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all sanyo semiconductor co.,ltd. products described or contained herein. sanyo semiconductor co.,ltd. strives to supply high-qua lity high-reliability products, however, any and all semiconductor products fail or malfunction with some probab ility. it is possible that these probabilistic failures or malfunction could give rise to accident s or events that could endanger human lives, trouble that could give rise to smoke or fire, or accidents that could cause damage to other property. when designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. upon using the technical information or products described herein, neither warranty nor license shall be granted with regard to intellectual property rights or any other rights of sanyo semiconductor co.,ltd. or any third party. sanyo semiconductor co.,ltd. shall not be liable for any claim or suits with regard to a third party's intellectual property rights which has resulted from the us e of the technical information and products mentioned above. information (including circuit diagrams and circuit par ameters) herein is for example only; it is not guaranteed for volume production. any and all information described or contained he rein are subject to change without notice due to product/technology improvement, etc. when designing equip ment, refer to the "delivery specification" for the sanyo semiconductor co.,ltd. product that you intend to use. in the event that any or all sanyo semiconductor co.,ltd. products described or contained herein are controlled under any of applicable local export control l aws and regulations, such products may require the export license from the authorities concerned in accordance with the above law. no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written consent of sanyo semiconductor co.,ltd.

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